The present invention relates generally to chopper-stabilized operational amplifiers. The invention also relates to chopper-stabilized operational amplifiers which include notch filters to reduce output ripple voltage due to the chopping signals. The invention relates more particularly to improvements which substantially reduce input bias current without necessarily decreasing chopping clock voltage level levels, without causing increased chopping-clock-induced ripple voltages, and/or without the need to increase notch filter capacitor size.
Chopper-stabilized operational amplifiers used as stand alone operational amplifiers provide excellent offset voltage and offset voltage drift performance without the need for trimming of components to reduce offset and drift. This means that in addition to good DC performance, chopper-stabilized operational amplifiers also have advantages of reduced integrated circuit die size and lower product cost. However, a major drawback of the known prior art chopper stabilization circuitry is the associated increased input bias current. (The term “input bias current” (not to be confused with the term “quiescent supply current”) refers only to the current required to flow into the signal path of the input terminals 7A and 7B, and it relates to matters such as generated noise and DC errors that react with the input source impedance. The input bias current is directly proportional to chopping clock frequency and also is dependent on the chopping clock voltage level and chopping switch types and sizes. Input bias current also is very dependent on integrated circuit layout and parasitics.)
The input bias current of a chopper-stabilized CMOS operational amplifier is significantly larger than that of a standard CMOS operational amplifier because of charge injection and clock feed-through induced from the input chopping switches.
It should be understood that the above mentioned charge injection occurs at the input chopping switches of a chopper-stabilized amplifier and results in a DC current component i.e., a DC offset, of the chopper-stabilized amplifier. An input chopping stage is coupled to two input terminals to which a differential input signal is applied, and that results in an injected charge flowing into or out of each of the two input terminals, respectively, at a rate proportional to the chopping frequency. Any mismatches in the chopping switches and/or associated parasitic elements cause a difference between the amount of injected charge that flows into and out of the two input terminals, respectively. If that difference in the injected charge is integrated over time, e.g., over any chopping period, a net amount of injected charge flows into or out of the two input terminals over any chopping cycle, and by definition, is a DC current or DC offset. Thus, relatively small spikes of current may be flowing into and out of each of the positive and negative input terminals, respectively of the chopper-stabilized amplifier. For example, if a positive current spike and the corresponding negative current spike are not precisely matched, there is a recurring “net current spike” that is integrated over time. That results in the above mentioned input bias current, which is a DC current. In this example, if a net current of 100 picoamperes flows into the positive input of the chopper-stabilized amplifier due to the above mentioned mismatches, there will be 100 picoamperes flowing out of the negative input (because of conservation of charge principles).
While the lowest possible chopping clock voltage level and smallest possible chopping switch size should always be used to minimize charge injection and clock feed-through, there is not much design flexibility for adjusting these two variables in order to meet certain design specifications, such as noise, speed, and signal level. Also, even though good integrated circuit layout practice should always be used to minimize parasitics, there is always random variation that contributes significantly to a distribution of the input bias current. Lowering the chopping frequency reduces input bias current, but leads to the need for larger filter capacitors to maintain a similar level of chopping ripple (i.e., chopping-clock-induced ripple or “ripple noise”) at the amplifier output.
It is highly desirable that integrated circuit operational amplifiers have low offset voltage, low noise, low offset drift, and good signal stability. Chopper stabilization and auto-zeroing are two common techniques that have been widely used to reduce amplifier offset voltage and drift. (For example, conventional chopper stabilization would typically reduce a 5 millivolt offset voltage to roughly 5 microvolts.) Modern chopper-stabilized operational amplifiers and auto-zero operational amplifiers have significantly reduced, or even essentially eliminated, the amount switching noise compared to previous designs. However, the improved design techniques used in modern chopper-stabilized operational amplifiers and auto-zero operational amplifiers result in trade-offs between input referred noise and quiescent supply current (Iq). The inherent trade-offs between basic chopper-stabilized amplifiers and auto-zero amplifiers are well known. While auto-zeroing methods provide low ripple noise at the amplifier output, its in-band noise is high due to aliasing or noise folding. On the other hand, chopper stabilization techniques present lower in-band noise due to absence of noise folding, but output ripple noise is relatively higher. Basic chopper-stabilized amplifiers maintain the broadband noise characteristics of their input stages but “shift” or modulate the input offset voltages up in frequency to the chopping frequency. This creates large ripple voltages at the amplifier outputs. Although basic auto-zero amplifiers do not shift their input offset to their auto-zero frequency like chopper-stabilized amplifiers, auto-zero amplifiers suffer from aliasing or folding back of their broadband noise spectrums during their zeroing cycles. This increases the overall input referred noise of auto-zero amplifiers.
It can be shown that for an ideal input stage, the square of the input referred noise is inversely proportional to the quiescent supply current Iq of the amplifier, which causes the basic auto-zero amplifiers to have significantly increased quiescent supply current Iq in order to achieve the desired noise levels, including the aliasing or noise folding. This makes it very desirable to use chopper-stabilized amplifiers in micropower applications and to find a way of solving the basic problem of ripple noise at the chopping frequency.
The closest prior art to the present invention is believed to include commonly owned U.S. Pat. No. 7,292,095 entitled “Notch Filter for Ripple Reduction in Chopper Stabilized Amplifiers” issued Nov. 6, 2007 to the present inventors, and incorporated herein by reference. Also see the related article by the present inventors entitled “A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter with Synchronous Integration inside the Continuous-Time Signal Path”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, December 2006. The closest prior art also is believed to include U.S. Pat. No. 6,262,626 entitled “Circuit Comprising Means for Reducing the DC-Offset and the Noise Produced by an Amplifier” issued Jul. 17, 2001 to Bakker et al.
Prior Art FIG. 1 herein is the same as FIG. 3A of the above mentioned '095 patent. In Prior Art FIG. 1, chopper stabilized amplifier 1C receives an input signal Vin and includes a first operational transconductance (i.e., with a voltage input and a current output) amplifier 2 having an input chopper 9 and an output chopper 10 for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter 15 filters the chopped output signal by operating synchronously with the chopping frequency of the output chopper stage to filter ripple voltages that otherwise would be produced by the output chopper stage. A second operational transconductance amplifier 3 amplifies the notch filter output. The input signal Vin is fed forward, summed with the output of the second operational transconductance amplifier 3, and applied to the input of a third operational transconductance amplifier or operational amplifier 4. Ripple noise and offset are substantially reduced.
Unfortunately, the chopper-stabilized amplifier in Prior Art FIG. 1 generates residual error on its inputs 7A and 7B due to charge injection from the chopping signal, and this results in an increase in input bias current. That is, averaging of the mismatches of chopper switch charge injection due to minute (e.g., roughly 10−13 farad) parasitic capacitances generates a DC bias current component that flows into one side of the chopping switches and out of the other side. Although decreasing the chopping clock frequency reduces the input bias current, it also results in increased ripple voltage or requires an unacceptable increase in the size of the notch filter capacitors. (Note that this would also be true for a continuous-time filter; that is, decreasing the chopping clock frequency would result in increased ripple voltage or would require an unacceptable increase in capacitances in the continuous-time filter.)
Prior Art FIG. 2 herein discloses an amplifier AMP as shown in FIG. 2 of the above mentioned '626 patent. Amplifier AMP in Prior Art FIG. 2 includes a pair of chopping switch circuits or “choppers” CHPi and CHPo for reducing the DC offset and the noise produced by amplifier AMP. To obtain optimal noise reduction, choppers CHPi and CHPo operate at a high frequency. As a result, the DC offset cancellation is not optimal because charge injection of the switches in choppers CHPi and CHPo produces a DC offset. To overcome this problem, amplifier AMP is provided with additional offset cancellation circuitry formed, for example, by another pair of choppers CHPfi, and CHPfo. Choppers CHPfi and CHPfo operate synchronously with choppers CHPfi and CHPfo but at a relatively low frequency. The combination of choppers CHPi and CHPo and additional choppers CHPfi and CHPfo ensures optimal DC offset cancellation. However, this technique, referred to as “nested chopping”, increases parasitics on the output affecting input offset voltage performance. Nevertheless, this results in better trade-offs between the ripple voltage sent to the next stage if chopping frequency is increased on choppers CHPi and CHPo and the lower residual offset voltage due to charge injection in the chopping switches that occurs if the chopping frequency is decreased on CHPfi and CHPfo.
There is an unmet need for a chopper-stabilized amplifier which has extremely low output ripple noise and which also has low input bias current.